1. Field of the Invention
The present invention relates to a semiconductor memory device such as static random access memory (SRAM).
2. Description of the Related Art
SRAM, which is one variety of semiconductor memory devices, does not require any refresh operation and thus can be used for implementing a simpler system with lower power consumption. That is why SRAM is suitable for use as memory in portable equipment such as cellular telephones. There is a demand for portable equipment that is even more compact, and the memory cell size of SRAM must be made smaller to address that demand.
An objective of the present invention is to provide a semiconductor memory device that makes it possible to reduce the size of memory cells.
One aspect of the present invention relates to a semiconductor memory device provided with a memory cell having an n-type first drive transistor, an n-type second drive transistor, a p-type first load transistor, a p-type second load transistor, an n-type first transfer transistor, and an n-type second transfer transistor, the semiconductor memory device comprising: a p-type well; an n-type well; a first conductive layer; a second conductive layer; a third conductive layer; and a fourth conductive layer, wherein:
the first conductive layer is formed on the p-type well and n-type well, the second conductive layer is formed on the first conductive layer, the third conductive layer is formed on the second conductive layer, and the fourth conductive layer is formed on the third conductive layer;
the first drive transistor, the second drive transistor, the first transfer transistor, and the second transfer transistor are positioned in the p-type well;
the first load transistor and the second load transistor are positioned in the n-type well;
a first gate electrode layer, a second gate electrode layer, and a sub word line are positioned in the first conductive layer;
a first drain-drain contact layer, a second drain-drain contact layer, a fist power line, a first contact pad layer, a second contact pad layer, and a third contact pad layer are positioned in the second conductive layer;
a first drain-gate contact layer, a second drain-gate contact layer, a main word line, a fourth contact pad layer, a fifth contact pad layer, and a sixth contact pad layer are positioned in the third conductive layer;
a first bit line, a second bit line, and a ground line are positioned in the fourth conductive layer;
the first gate electrode layer includes gate electrodes of the first drive transistor and the first load transistor
the second gate electrode layer includes gate electrodes of the second drive transistor and the second load transistor;
the sub word line extends in the first direction;
the first drain-drain contact layer connects a drain of the first drive transistor to a drain of the first load transistor;
the second drain-drain contact layer connects a drain of the second drive transistor to a drain of the second load transistor
the first and the second gate electrode layers are positioned between the first drain-drain contact layer and the second drain-drain contact layer, as seen in plan view of the memory cell;
the first power line is connected to a well contact region of the n-type well, a source of the first load transistor, and a source of the second load transistor;
the first contact pad layer is used for connecting the first bit line to a source/drain region of the first transfer transistor;
the second contact pad layer is used for connecting the second bit line to a source/drain region of the second transfer transistor;
the third contact pad layer is used for connecting a well contact region of the p-type well, a source of the first drive transistor, and a source of the second drive transistor to the ground line;
the first drain-gate contact layer connects the first drain-drain contact layer to the second gate electrode layer;
the second drain-gate contact layer connects the second drain-drain contact layer to the first gate electrode layer;
the main word line extends in the first direction;
the fourth contact pad layer is used for connecting the first bit line to the source/drain region of the first transfer transistor;
the fifth contact pad layer is used for connecting the second bit line to the source/drain region of the second transfer transistor;
the sixth contact pad layer is used for connecting the well contact region of the p-type well, the source of the first drive transistor, and the source of the second drive transistor to the ground line;
the first bit line extends in a second direction that crosses the first direction at right angle; and
the second bit line extends in the second direction.
This aspect of the present invention is further provided with a gate electrode layer that forms gates of inverters, a drain-drain contact layer connecting together the drains of the inverters, and a drain-gate contact layer connecting the gate of one inverter to the drain of the other inverter. Three layers (a gate electrode layer, a drain-drain contact layer, and a drain-gate contact layer) are used in the fabrication of the flip-flop in accordance with the present invention. This makes it possible to simplify the pattern of each layer (by making them linear, by way of example), in comparison with a flip-flop formed by using two layers. Since the present invention makes it possible to simplify the pattern of each layer, it is therefor possible to create a semiconductor memory device having a memory cell size with dimensions of 4.5 xcexcm2 or less.
The first and the second gate electrode layers are positioned between the first drain-drain contact layer and the second drain-drain contact layer, as seen in plan view of the memory cell. It is therefore possible to dispose the source contact layer of the drive transistors and the third contact pad layer in the center of the memory cell. This increases the degree of freedom in forming the first and the second drain-gate contact layers, which further helps in reducing the memory cell size. Note that the source contact layer in accordance with the present invention is a conductive layer that is used for connecting the source of the drive transistor to a wiring layer.
The present invention disposes the conductive layers that are necessary for the structure of the semiconductor memory device in a well-balanced manner. It is therefore possible to improve the various attributes required of the semiconductor memory device, such as compact dimensions, reliability, stability, and speed.
This aspect of the present invention may further comprise a second power line, and the second power line may be disposed in the vicinity of the memory cell, the second power line may be positioned in the fourth conductive layer, and the second power line may be connected to the first power line. This aspect of the present invention makes it possible to reduce the resistance of the wiring between the power line and the n-type well of the memory cell, thus making it difficult for latch-up to occur.
The second power line may extend in the second direction, the first power line may extend in the first direction, the first power line may overlap the main word line on a different level, the first power line may have a branch portion that extends in the second direction, a seventh contact pad layer may be positioned in the third conductive layer, and the branch portion and the seventh contact pad layer may be used for connecting the first power line to the second power line. By providing such a branch line, the first power line can be connected to the second power line, even if the first power line overlaps the main word line, as seen in plan view of the memory cell. The seventh contact pad layer and the branch portion may be positioned above the well contact region of the n-type well. The memory cell is not formed above the the well contact region of the n-type well. Thus the present invention makes it possible to form the seventh contact pad layer and the branch portion without wasting space in the memory cell region. The present invention therefore makes it possible to ensure that the only wire that is necessary for fixing the potential of the n-type well is the second power line disposed in the vicinity of the memory cell, thus implementing a highly reliable semiconductor memory device without disturbing the miniaturization of the memory cell. Note that the n-type well contact region and the second power line could be disposed for each 32 cells or 64 cells, by way of example.
The first power line may extend in the first direction. Furthermore, the ground line may extend in the second direction. The first and the second gate electrode layers in accordance with the present invention may extend in the second direction. The first and the second drain-drain contact layers in accordance with the present invention may extend in the second direction. The third contact pad layer in accordance with the present invention may extend in the second direction.
The first gate electrode layer, the second gate electrode layer, the first drain-drain contact layer, and the second drain-drain contact layer may be disposed in parallel to one another and may each be formed in a linear pattern. The present invention makes it possible to simplify the patterning and thus fabricate a semiconductor memory device with a very small memory cell size.